computer organization and design suppose we have a program with those instructions a 5150467
Computer Organization And Design
Suppose we have a program with those instructions.
ADD/NAND 35%, BEQ 15%, SW 20%, LW 30%
The hit rate of I-cache is 80%. The hit rate of D-cache is 90%. Branch predictor is used, and 70% of branches are predicted correctly. Memory access time is 100ns. Supposing that Branch outcome would be decided in MEM stage. If the prediction is ‘not taken’, the loss is 0. When the prediction is wrong, new Fetch is possible at the same cycle with WB stage of that branch instruction. (resolve is performed in MEM stage)
(1) If the target processor is 100MHz, 5-stage pipelined architecture and support full forwarding, what would be the CPI? Suppose that 35% of lw instructions have dependent instruction at the very next which uses the result. (lw-use)
(2) Change its architecture that EX stage has 3 sub stage, so now it is 7-stage pipelined architecture. When all needed forwarding is implemented, its frequency is 200MHz. What would be the CPI?
*Here, RAW dependency is below.
– 35% of lw instructions have dependent instruction at the very next which uses the result. (lw-use)
– For 5% of lw instructions (irrelevant to above 35%), third next instruction uses the result of lw. (lw-x-y-use, where x and y are independent instructions)